In the feedback system shown below $${\rm{G(s) = }}{1 \over {\left( {s + 1} \right)\left( {s + 2} \right)\left( {s + 3} \right)}}$$ The positive value of 𝑘 for which the gain margin of the loop is exactly 0 dB and the phase margin of the loop is exactly zero degree is ____

Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor 𝑅 = 10 𝑘Ω and the supply voltage is 5 𝑉. The D flip-flops D₁, D₂, D₃, D₄ and D₅ are initialized with logic values 0, 1, 0,1 and 0, respectively. The clock has a 30% duty cycle.

The average power dissipated (in mW) in resistor R is ______.

The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is shown in the figure.

Which one of the following statements is correct?

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a