1
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+1
-0.3
Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor C. This design is to be converted to that of a NOR circuit in the same technology, so that its worst case charge and discharge times while driving the same capacitor are similar. The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct? GATE ECE 2016 Set 2 Electronic Devices and VLSI - IC Basics and MOSFET Question 44 English
A
Widths of PMOS transistors should be doubled, while widths of NMOS transistors should be halved.
B
Widths of PMOS transistors should be doubled, while widths of NMOS transistors should not be changed.
C
Widths of PMOS transistors should be halved, while widths of NMOS transistors should not be changed.
D
Widths of PMOS transistors should be unchanged, while widths of NMOS transistors should be halved.
2
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A voltage VG is applied across a MOS capacitor with metal gate and p-type silicon substrate at T=300 K. The inversion carrier density (in number of carriers per unit area) for VG = 0.8 V is $$2\,\, \times \,\,{10^{11}}\,\,\,\,\,\,c{m^{ - 2}}$$ . For $${V_G}\,\, = \,\,1.3\,\,V,$$ the inversion carrier density is $$4\,\,\, \times \,\,\,{10^{11}}\,\,\,\,c{m^{ - 2}}.$$ What is the value of the inversion carrier density for VG = 1.8 V?
A
$$4.5 \times {10^{11}}\,\,c{m^{ - 2}}$$
B
$$6.0 \times {10^{11}}\,\,c{m^{ - 2}}$$
C
$$7.2 \times {10^{11}}\,\,c{m^{ - 2}}$$
D
$$8.4 \times {10^{11}}\,\,c{m^{ - 2}}$$
3
GATE ECE 2016 Set 2
Numerical
+2
-0
Consider a long-channel NMOS transistor with source and body connected together. Assume that the electron mobility is independent of VGS and VDS. Given,
gm = 0.5$$\mu {\rm A}/V$$ for VDS = 50 m V and VGS = 2V,
gd = $$8\mu {\rm A}/V$$ for VGS = 2 V and VDS = 0 V,
Where gm =$${{\partial {{\rm I}_D}} \over {\partial {V_{GS}}}}\,\,and\,\,{g_d}\,\, = \,{{\partial {{\rm I}_D}} \over {\partial {V_{DS}}}}$$

The threshold voltage (in volts) of the transistor is

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4
GATE ECE 2016 Set 2
Numerical
+1
-0
The value of $$x$$ for which the matrix $$A = \left[ {\matrix{ 3 & 2 & 4 \cr 9 & 7 & {13} \cr { - 6} & { - 4} & { - 9 + x} \cr } } \right]$$ has zero as an eigen value is __________.
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