1
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+1
-0.3
A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while 𝐶in is the input carry and 𝐶out is the output carry. A and B are to be used as the select bits with A being the more significant select bit. GATE ECE 2016 Set 2 Digital Circuits - Combinational Circuits Question 35 English Which one of the following statements correctly describes the choice of signals to be connected to the inputs $${I_0}$$, $${I_1}$$, $${I_2 }$$ and $${I_3}$$ so that the output is C$$_{out}$$?
A
$${I_0} = 0,{I_0} = {C_{in}},\,{I_{2\,}} = {C_{in}}\,and\,{I_3} = I$$
B
$${I_0} = 1,\,{I_1}\, = {C_{in}},\,{I_{2\,}} = {C_{in}}\,and\,{I_3} = I$$
C
$${I_0} = {C_{in}},\,\,{I_{1\,}} = 0,\,{I_{2\,}} = 1and\,{I_3} = \,{C_{in}}$$
D
$${I_0} = 0,{I_1} = {C_{in}},\,{I_{2\,}} = \,2and\,{I_3} = {C_{in}}\,$$
2
GATE ECE 2016 Set 2
Numerical
+1
-0
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor 𝑅 = 10 𝑘Ω and the supply voltage is 5 𝑉. The D flip-flops D1, D2, D3, D4 and D5 are initialized with logic values 0, 1, 0,1 and 0, respectively. The clock has a 30% duty cycle. GATE ECE 2016 Set 2 Digital Circuits - Sequential Circuits Question 48 English

The average power dissipated (in mW) in resistor R is ______.

Your input ____
3
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is shown in the figure. GATE ECE 2016 Set 2 Digital Circuits - Sequential Circuits Question 22 English

Which one of the following statements is correct?

A
Transitions from State A are ambiguously defined.
B
Transitions from State B are ambiguously defined.
C
Transitions from State C are ambiguously defined.
D
All of the state transitions are defined unambiguously.
4
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+2
-0.6
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero GATE ECE 2016 Set 2 Digital Circuits - Sequential Circuits Question 21 English

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

A
mod-5 counter
B
mod-6 counter
C
mod-7 counter
D
mod-8 counter
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