1
GATE ECE 2016 Set 2
Numerical
+1
-0
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor 𝑅 = 10 𝑘Ω and the supply voltage is 5 𝑉. The D flip-flops D1, D2, D3, D4 and D5 are initialized with logic values 0, 1, 0,1 and 0, respectively. The clock has a 30% duty cycle. GATE ECE 2016 Set 2 Digital Circuits - Sequential Circuits Question 48 English

The average power dissipated (in mW) in resistor R is ______.

Your input ____
2
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is shown in the figure. GATE ECE 2016 Set 2 Digital Circuits - Sequential Circuits Question 22 English

Which one of the following statements is correct?

A
Transitions from State A are ambiguously defined.
B
Transitions from State B are ambiguously defined.
C
Transitions from State C are ambiguously defined.
D
All of the state transitions are defined unambiguously.
3
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+2
-0.6
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero GATE ECE 2016 Set 2 Digital Circuits - Sequential Circuits Question 21 English

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

A
mod-5 counter
B
mod-6 counter
C
mod-7 counter
D
mod-8 counter
4
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+2
-0.6
In an N bit flash ADC, the analog voltage is fed simultaneously to 2N− 1 comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source Vin(whose output is being converted to digital format) has a source resistance of 75 Ω as shown in the circuit diagram below and the input capacitance of each comparator is 8 pF. The input must settle to an accuracy of 1/2 LSB even for a full scale input change for properconversion. Assume that the time taken by the thermometer to binary encoder is negligible. GATE ECE 2016 Set 2 Digital Circuits - Analog to Digital and Digital to Analog Converters Question 7 English If the flash ADC has 8 bit resolution, which one of the following alternatives is closest to the maximum sampling rate?
A
1 megasamples per second
B
6 megasamples per second
C
64 megasamples per second
D
256 megasamples per second
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