The state transition matrix $$\phi \left( t \right)$$ of a system $$$\left[ {\matrix{ {\mathop {{x_1}}\limits^ \bullet } \cr {\mathop {{x_2}}\limits^ \bullet } \cr } } \right] = \left[ {\matrix{ 0 & 1 \cr 0 & 0 \cr } } \right]\left[ {\matrix{ {{x_1}} \cr {{x_2}} \cr } } \right] is$$$

In the circuit shown in the figure, if C = 0, the expression for Y is

A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be_______________.

An 8-to-1 multiplexer is used to implement a logical function Y as shown in the figure. The output Y is given by