1
GATE ECE 2014 Set 4
MCQ (Single Correct Answer)
+1
-0.3
In a Bode magnitude plot, which one of the following slopes would be exhibited at high frequencies by a 4th order all-pole system?
A
– 80 dB/decade
B
– 40 dB/decade
C
+40 dB/decade
D
+80 dB/decade
2
GATE ECE 2014 Set 4
MCQ (Single Correct Answer)
+2
-0.6
The state transition matrix $$\phi \left( t \right)$$ of a system $$$\left[ {\matrix{ {\mathop {{x_1}}\limits^ \bullet } \cr {\mathop {{x_2}}\limits^ \bullet } \cr } } \right] = \left[ {\matrix{ 0 & 1 \cr 0 & 0 \cr } } \right]\left[ {\matrix{ {{x_1}} \cr {{x_2}} \cr } } \right] is$$$
A
$$\left[ {\matrix{ t & 1 \cr 1 & 0 \cr } } \right]$$
B
$$\left[ {\matrix{ 1 & 0 \cr t & 1 \cr } } \right]$$
C
$$\left[ {\matrix{ 0 & 1 \cr 1 & t \cr } } \right]$$
D
$$\left[ {\matrix{ 1 & t \cr 0 & 1 \cr } } \right]$$
3
GATE ECE 2014 Set 4
MCQ (Single Correct Answer)
+1
-0.3
In the circuit shown in the figure, if C = 0, the expression for Y is GATE ECE 2014 Set 4 Digital Circuits - Logic Gates Question 19 English
A
Y= $$A\overline B + \overline A B$$
B
Y=A+B
C
Y= $$\,\overline A \, \overline B $$
D
Y=A B
4
GATE ECE 2014 Set 4
Numerical
+2
-0
A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be_______________. GATE ECE 2014 Set 4 Digital Circuits - Combinational Circuits Question 21 English
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