GATE ECE 2014 Set 4 | GATE ECE Year Wise Previous Years Questions

GATE ECE 2014 Set 4

Numerical

-0

A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be_______________. GATE ECE 2014 Set 4 Digital Circuits - Combinational Circuits Question 28 English

Your input ____

GATE ECE 2014 Set 4

MCQ (Single Correct Answer)

-0.6

An 8-to-1 multiplexer is used to implement a logical function Y as shown in the figure. The output Y is given by GATE ECE 2014 Set 4 Digital Circuits - Combinational Circuits Question 29 English

GATE ECE 2014 Set 4 Digital Circuits - Combinational Circuits Question 29 English

Y= A$$\overline B \,C + A\overline C D$$

$$Y = \overline A BC + A\overline B D$$

$$Y = AB\overline C + \overline A CD$$

$$Y = \overline A \,\overline B D + A\overline B C$$

GATE ECE 2014 Set 4

MCQ (Single Correct Answer)

-0.3

The output (Y) of the circuit shown in the figure is GATE ECE 2014 Set 4 Digital Circuits - Logic Families Question 9 English

$$\overline A + \overline B + \overline C $$

$$A + \overline B \,\overline {.\,C} + A.\,\overline C $$

$$\overline A + B + \overline C $$

$$A.B.\overline C $$

GATE ECE 2014 Set 4

MCQ (Single Correct Answer)

-0.3

Match column A with column B.

Column
1. Point electromagnetic source
2. Dish antenna
3. Yagi-Uda antenna

Column
P. Highly directional
Q. End fire
R. Isotropic

1 = P, 2 = Q, 3 = R

1 = R, 2 = P, 3 = Q

1 = Q, 2 = P, 3 = R

1 = R, 2 = Q, 3 = P

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