The inputs to a digital circuit shown in Figure 9(a) are the external signals A, B and C. ( $$\overline A \,\overline B \,and\,\overline {C\,} $$ and are not available). The +5V power supply (logic 1) and the ground (logic 0) are also available. The output of the circuit is X = $$\overline A \,B + \,\overline A \,\overline B \,\,\overline {C\,} $$
(a) Write down the output function in its canonical SOP and POS forms.
(b) Implement the circuit using only two 2:1 multiplexers shown in the Figure where S is the data-select line, $${D_0}\,$$ and $${D_1}\,$$ are the input data lines and Y is the output lines. The function table for the multiplexer is given in table

If the input X$$_3$$, X$$_2$$, X$$_1$$, X$$_0$$ to the ROM in figure 2.12 are 8-4-2-1 BCD numbers, then the outpus are Y$$_3$$,Y$$_2$$, Y$$_1$$, Y$$_0$$ are

The number of comparators required in a 3-bit comparator type ADC is

It is required to design a binary mod-5 synchronus counter using AB flip-flops such that the output Q₂Q₁Q₀ changes as $$000 \to 001 \to 010$$ ........and so on. The excitation table for the AB flip-flops is given in the table

(a) Write down the state table for the mod-5 counter.
(b)Obtain simplified SOP expressions for the inputs A₂, B₂, A₁, B₁, A₀ and B₀ in terms of Q₂, Q₁, Q and their complements.
(c) Hence, complete the circuit diagram for the mod-5 counter given in the figure using minimum number of 2-input NAND-gate only.