1

### NEET 2016 Phase 2

For CE transistor amplifier, the aufio signal voltage across the collector resistance of 2 k$\Omega$ is 4 V. If the current amplification factor of the transistor is 100 and the base resistance is 1 k$\Omega$, then the input signal voltage is
A
10 mV
B
20 mV
C
30 mV
D
15 mV

## Explanation

Voltage gain, A = $\beta {{{R_C}} \over {{R_B}}}$ = $100 \times {{2000} \over {1000}}$ = 200

Also, A = ${{{V_0}} \over {{V_i}}}$

$\Rightarrow$ ${V_i} = {{{V_0}} \over A}$ = ${4 \over {200}}$ = 20 mA
2

### AIPMT 2015 Cancelled Paper

If in a p-n junction, a square input signal of 10 V is applied, as shown, then the output across RL will be
A B C D ## Explanation

Here P-N junction diode rectifies half of the ac wave i.e., acts as half wave rectifier.
During + ve half cycle Diode is forward biased output across RL will be During –ve half cycle Diode is reverse biased output will not obtained.
3

### AIPMT 2015 Cancelled Paper

Which logic gate is represented by the following combination of logic gates ? A
AND
B
NOR
C
OR
D
NAND

## Explanation

The Boolean expression of this arrangement is

Y = $\overline {\overline A + \overline B }$ = $\overline{\overline A} + \overline{\overline B}$ = A.B

Thus, the combination represents AND gate.
4

### AIPMT 2015

In the given figure, a diode D is connected to an external resistance R = 100 $\Omega$ and an e.m.f. of 3.5 V. If the barrier potential developed across the diode is 0.5 V, the current in the citcuit will be A
20 mA
B
35 mA
C
30 mA
D
40 mA

## Explanation

Potential difference across resistance R

= 3.5 – 0.5 = 3.0 V

Current in circuit, I = V/R = 3/100 = 30 mA