1
MHT CET 2023 9th May Morning Shift
MCQ (Single Correct Answer)
+1
-0
To get the truth table shown, from the following logic circuit, the Gate G should be
2
MHT CET 2022 11th August Evening Shift
MCQ (Single Correct Answer)
+1
-0
For a NAND gate, the inputs and outputs are given below.
| Input A | Input B | Output Y |
|---|---|---|
| 0 | 1 | $$\mathrm{C}$$ |
| 0 | 0 | $$\mathrm{D}$$ |
| 1 | 0 | $$\mathrm{E}$$ |
| 1 | 1 | $$\mathrm{F}$$ |
The values taken by C, D, E, F are respectively
3
MHT CET 2022 11th August Evening Shift
MCQ (Single Correct Answer)
+1
-0
The given circuit has two ideal diodes $$D_1$$ and $$D_2$$ connected as shown in the figure. The current flowing through the resistance $$R_1$$ will be
4
MHT CET 2021 24th September Evening Shift
MCQ (Single Correct Answer)
+1
-0
Choose the correct statement. In conductors
Questions Asked from Semiconductor Devices and Logic Gates (MCQ (Single Correct Answer))
Number in Brackets after Paper Indicates No. of Questions
MHT CET 2023 14th May Evening Shift (3)
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MHT CET 2023 13th May Morning Shift (3)
MHT CET 2023 12th May Evening Shift (3)
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MHT CET 2023 11th May Evening Shift (3)
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MHT CET 2023 9th May Evening Shift (3)
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MHT CET 2022 11th August Evening Shift (2)
MHT CET 2021 24th September Evening Shift (3)
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MHT CET 2021 23rd September Evening Shift (3)
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MHT CET 2021 22th September Evening Shift (3)
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MHT CET 2020 19th October Evening Shift (2)
MHT CET 2020 16th October Evening Shift (2)
MHT CET 2020 16th October Morning Shift (2)
MHT CET 2019 3rd May Morning Shift (2)
MHT CET 2019 2nd May Evening Shift (2)
MHT CET 2019 2nd May Morning Shift (2)
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