1
GATE CSE 2024 Set 1
MCQ (More than One Correct Answer)
+1
-0.33

Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the following statements about the circuit is/are CORRECT?

GATE CSE 2024 Set 1 Digital Logic - Combinational Circuits Question 3 English
A

With no propagation delays, the output Y is always logic Zero

B

With no propagation delays, the output Y is always logic One

C

With propagation delays, the output Y can have a transient logic One after X transitions from logic Zero to logic One

D

With propagation delays, the output Y can have a transient logic Zero after X transitions from logic One to logic Zero

2
GATE CSE 2021 Set 2
MCQ (Single Correct Answer)
+1
-0.33

Which one of the following circuits implements the Boolean function given below?

f(x, y,z) = m0 + m1 + m3 +m4 + m5 + m6, where mi is the ith minterm.

A
GATE CSE 2021 Set 2 Digital Logic - Combinational Circuits Question 4 English Option 1
B
GATE CSE 2021 Set 2 Digital Logic - Combinational Circuits Question 4 English Option 2
C
GATE CSE 2021 Set 2 Digital Logic - Combinational Circuits Question 4 English Option 3
D
GATE CSE 2021 Set 2 Digital Logic - Combinational Circuits Question 4 English Option 4
3
GATE CSE 2020
Numerical
+1
-0.33
A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____.
Your input ____
4
GATE CSE 2020
Numerical
+1
-0.33
If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ____.
Your input ____
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