1
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+1
-0.3
The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ($$\overline {{R_d}} $$ input). The counter corresponding to this circuit is GATE ECE 2015 Set 3 Digital Circuits - Sequential Circuits Question 51 English
A
a modulo-5 binary up counter
B
a modulo-6 binary down counter
C
a modulo-5 binary down counter
D
a modulo-6 binary up counter
2
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+2
-0.6
A three bit pseudo random number generator is shown. Initially the value of output Y = Y2 Y1 Y0 is set to 111. The value of output Y after three clock cycles is GATE ECE 2015 Set 3 Digital Circuits - Sequential Circuits Question 29 English
A
000
B
001
C
010
D
100
3
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+2
-0.6
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing GATE ECE 2015 Set 3 Digital Circuits - Sequential Circuits Question 28 English
A
NOR gates to NAND gates
B
inverts to buffers
C
NOR gates to NAND gates and inverters to buffers
D
5 V to ground
4
GATE ECE 2015 Set 3
Numerical
+2
-0
A 200 m long transmission line having parameters shown in the figure is terminated into a load ܴ$$R_L$$. The line is connected to a 400 V source having source resistance $$R_S$$ through a switch, which is closed at t = 0. The transient response of the circuit at the input of the line (z = 0) is also drawn in the figure. The value of ܴ$$R_L$$ (in $$\Omega $$ ) is ___________. GATE ECE 2015 Set 3 Electromagnetics - Transmission Lines Question 7 English
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