The circuit diagram of a synchronous counter is shown in the figure. Determine the sequence of states of the counter assuming that the initial state is ‘000’. Give your answer in a tabulor form showing the present state Q_A(n), Q_B(n), Q_C(n), J-K inputs ( J_A, K_A, J_B, K_B, J_C, K,) and the next state $${Q_{A\left( {n + 1} \right)}},\,{Q_{B\left( {n + 1} \right)}},{Q_{C\left( {n + 1} \right)}}$$ From the table, determine the modulus of the counter.

In certain application, four inputs A, B, C, D (both true and complement forms available)are fed to logic circuit, producing an output F which operates a relay. The relay turns on when F(ABCD)=1 for the following states of the inputs (ABCD):'0000', '0010' ,0101',0110','1101' and '1110'. States '1000' and '1001' do not occur, and for the remaining states, the relay is off. Minaining states, the relay is off. Minimize F with the help of a Karnaugh map and realize it using a minimum number of 3- input NAND gates.

The Logical expression $$Y = A + \overline A B$$ is equivalent to

For a binary half-subtractor having two inputs A and B, the correct set of Logical expressions for the output D(=Aminus B) and X(=Borrow) are