GATE CSE 2026 Set 1 | Machine Instructions and Addressing Modes Question 2 | Computer Organization

GATE CSE 2026 Set 1

MCQ (Single Correct Answer)

-0

Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II:

List-I		List-II
P.	Immediate	1.	Element of an array
Q.	Indirect	2.	Pointer
R.	Base with index	3.	Element of a record
S.	Base with offset/displacement	4.	Constant

$\mathrm{P}-4, \mathrm{Q}-3, \mathrm{R}-1, \mathrm{~S}-2$

$P-4, Q-2, R-1, S-3$

$P-1, Q-4, R-3, S-2$

$\mathrm{P}-2, \mathrm{Q}-3, \mathrm{R}-1, \mathrm{~S}-4$

GATE CSE 2026 Set 1

MCQ (Single Correct Answer)

-0

Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand.

Which one of the following sequences of instructions corresponds to the high-level language statement $Z=X+Y$ ?

Note: $X, Y$, and $Z$ are memory operands. $R 0, R 1$, and $R 2$ are registers.

ADD Z, X, Y

ADD RO, X, Y STORE Z, R0

LOAD RO, X

ADD Z, RO, Y

LOAD RO, X

LOAD R1, Y

ADD R2, R0, R1

STORE Z, R2

GATE CSE 2025 Set 2

MCQ (More than One Correct Answer)

-0.33

Which of the following is/are part of an Instruction Set Architecture of a processor?

The size of the cache memory

The clock frequency of the processor

The number of cache memory levels

The total number of registers

GATE CSE 2020

MCQ (Single Correct Answer)

-0.33

Consider the following statements.

I. Daisy chaining is used to assign priorities in attending interrupts.

II. When a device raises a vectored interrupt, the CPU does polling to identify the source of the interrupt.

III. In polling, the CPU periodically checks the status bits to know if any device needs its attention.

IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.

Which of the above statements is/are TRUE?

I and IV only

I and II only

III only

I and III only