GATE CSE 2016 Set 2 | Machine Instructions and Addressing Modes Question 5 | Computer Organization

GATE CSE 2016 Set 2

Numerical

-0

A processor has $$40$$ distinct instructions and $$24$$ general purpose registers. A $$32$$-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is __________ .

Your input ____

GATE CSE 2015 Set 1

MCQ (Single Correct Answer)

-0.3

For computers based on three-address instruction formats, each address field can be used to specify which of the following:

(S1) A memory operand
(S2) A processor register
(S3) An implied accumulator register

Either S1 or S2

Either S2 or S3

Only S2 and S3

All of S1, S2 and S3

GATE CSE 2006

MCQ (Single Correct Answer)

-0.3

A $$CPU$$ has $$24$$-bit instructions. A program starts at address $$300$$ (in decimal). Which one of the following is a legal program counter (all values in decimal)?

$$400$$

$$500$$

$$600$$

$$700$$

GATE CSE 2004

MCQ (Single Correct Answer)

-0.3

Which of the following addressing modes are suitable for program relocation at run time?
$$1.$$ Absolute addressing
$$2.$$ Based addressing
$$3.$$ Relative addressing
$$4.$$ Indirect addressing

$$1$$ and $$4$$

$$1$$ and $$2$$

$$2$$ and $$3$$

$$1, 2$$ and $$4$$

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GATE CSE Subjects

Theory of Computation

Undecidability Finite Automata and Regular Language Push Down Automata and Context Free Language Recursively Enumerable Language and Turing Machine

Operating Systems

Process Concepts and Cpu Scheduling Synchronization and Concurrency File System IO and Protection Deadlocks Memory Management

Algorithms

Complexity Analysis and Asymptotic Notations Searching and Sorting Divide and Conquer Method Greedy Method P and NP Concepts Dynamic Programming