1
GATE CSE 2020
MCQ (Single Correct Answer)
+1
-0.33
Consider the following statements.

I. Daisy chaining is used to assign priorities in attending interrupts.
II. When a device raises a vectored interrupt, the CPU does polling to identify the source of the interrupt.
III. In polling, the CPU periodically checks the status bits to know if any device needs its attention.
IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.

Which of the above statements is/are TRUE?
A
I and IV only
B
I and II only
C
III only
D
I and III only
2
GATE CSE 2020
MCQ (Single Correct Answer)
+1
-0.33
Consider the following data path diagram. GATE CSE 2020 Computer Organization - Machine Instructions and Addressing Modes Question 2 English
Consider an instruction: R0 $$ \leftarrow $$ R1 + R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively.

1. R2r, TEMP1r, ALUadd, TEMP2w
2. R1r, TEMP1w
3. PCr, MARw, MEMr
4. TEMP2r, R0w
5. MDRr, IRw

Which one of the following is the correct order of execution of the above steps?
A
3, 5, 1, 2, 4
B
3, 5, 2, 1, 4
C
1, 2, 4, 3, 5
D
2, 1, 4, 5, 3
3
GATE CSE 2016 Set 2
Numerical
+1
-0
A processor has $$40$$ distinct instructions and $$24$$ general purpose registers. A $$32$$-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is __________ .
Your input ____
4
GATE CSE 2015 Set 1
MCQ (Single Correct Answer)
+1
-0.3
For computers based on three-address instruction formats, each address field can be used to specify which of the following:

(S1) A memory operand
(S2) A processor register
(S3) An implied accumulator register

A
Either S1 or S2
B
Either S2 or S3
C
Only S2 and S3
D
All of S1, S2 and S3
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