1
GATE CSE 2022
+1
-0.33

Let R1 and R2 be two 4-bit registers that store numbers in 2's complement form. For the operation R1 + R2, which one of the following values of R1 and R2 gives an arithmetic overflow?

A
R1 = 1011 and R2 = 1110
B
R1 = 1100 and R2 = 1010
C
R1 = 0011 and R2 = 0100
D
R1 = 1001 and R2 = 1111
2
GATE CSE 2022
+1
-0.33

Consider three floating points numbers A, B and C stored in registers RA, RB and RC, respectively as per IEEE-754 single precision floating point format. The 32-bit content stored in these registers (in hexadecimal form) are as follows.

Which one of the following is FALSE?

A
A + C = 0
B
C = A + B
C
B = 3C
D
(B $$-$$ C) > 0
3
GATE CSE 2019
+1
-0.33
In 16-bit 2's complement representation, the decimal number -28 is :
A
1000 0000 1110 0100
B
0000 0000 1110 0100
C
1111 1111 1110 0100
D
1111 1111 0001 1100
4
GATE CSE 2019
+1
-0.33
Consider Z = X - Y, where X, Y and Z are all in sign-magnitude form. X and Y are each represented in n bits. To avoid overflow, the representation of Z would require a minimum of:
A
n + 1 bits
B
n – 1 bits
C
n + 2 bits
D
n bits
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