1
GATE CSE 2022
MCQ (Single Correct Answer)
+1
-0.33
Let R1 and R2 be two 4-bit registers that store numbers in 2's complement form. For the operation R1 + R2, which one of the following values of R1 and R2 gives an arithmetic overflow?
2
GATE CSE 2022
MCQ (Single Correct Answer)
+1
-0.33
Consider three floating points numbers A, B and C stored in registers RA, RB and RC, respectively as per IEEE-754 single precision floating point format. The 32-bit content stored in these registers (in hexadecimal form) are as follows.
Which one of the following is FALSE?
3
GATE CSE 2019
MCQ (Single Correct Answer)
+1
-0.33
In 16-bit 2's complement representation, the decimal number -28 is :
4
GATE CSE 2019
MCQ (Single Correct Answer)
+1
-0.33
Consider Z = X - Y, where X, Y and Z are all in sign-magnitude form. X and Y are each represented in n bits. To avoid overflow, the representation of Z would require a minimum of:
Questions Asked from Number Systems (Marks 1)
Number in Brackets after Paper Indicates No. of Questions
GATE CSE 2024 Set 2 (1)
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Discrete Mathematics
Programming Languages
Theory of Computation
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