1
GATE CSE 2022
Numerical
+2
-0

Consider a demand paging system with four page frames (initially empty) and LRU page replacement policy. For the following page reference string

7, 2, 7, 3, 2, 5, 3, 4, 6, 7, 7, 1, 5, 6, 1

the page fault rate, defined as the ratio of number of page faults to the number of memory accesses (rounded off to one decimal place) is _____________.

Your input ____
2
GATE CSE 2021 Set 2
Numerical
+2
-0

Consider a three-level page table to translate a 39-bit virtual address to a physical address as shown below.

GATE CSE 2021 Set 2 Operating Systems - Memory Management Question 9 English

The page size is 4 KB (1 KB = 210 bytes) and page table entry size at every level is 8 bytes. A process P is currently using 2 GB (1 GB = 230 bytes) virtual memory which is mapped to 2 GB of physical memory. The minimum amount of memory required for the page table of P across all levels is _______ KB.

Your input ____
3
GATE CSE 2020
Numerical
+2
-0
Consider a paging system that uses a 1-level page table residing in main memory and a TLB for address translation. Each main memory access takes 100 ns and TLB lookup takes 20 ns. Each page transfer to/from the disk takes 5000 ns. Assume that the TLB hit ratio is 95%, page fault rate is 10%. Assume that for 20% of the total page faults, a dirty page has to be written back to disk before the required page is read in from disk. TLB update time is negligible. The average memory access time in ns (round off to 1 decimal places) is ______.
Your input ____
4
GATE CSE 2019
MCQ (Single Correct Answer)
+2
-0.67

Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 8 kB and the word size is 4 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 128 valid entries. At most how many distinct virtual addresses can be translated without any TLB miss?

A
16 × 210
B
8 × 220
C
4 × 220
D
256 × 210
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