1
GATE EE 2021
Numerical
+2
-0
A CMOS Schmitt-trigger inverter has a low output level of 0 V and a high output level of 5 V . It has input thresholds of 1.6 V and 2.4 V . The input capacitance and output resistance of the Schmitt trigger are negligible. The frequency of the oscillator shown in the figure is $\_\_\_\_$ Hz. (Round off to 2 decimal places)

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2
GATE EE 2014 Set 2
Numerical
+2
-0
An oscillator circuit using ideal op-amp and diodes is shown in the figure.
The duration for $$+ve$$ part of the cycle $$\Delta {t_1}$$ and for $$-ve$$ part is $$\Delta {t_2}.$$ The value of $$e$$ $${{\Delta {t_2} - \Delta {t_1}} \over {RC}}$$ will be _______.
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3
GATE EE 2012
MCQ (Single Correct Answer)
+2
-0.6
The circuit shown is a
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