1
GATE CSE 2006
MCQ (Single Correct Answer)
+2
-0.6
Given two three bit number $${a_2}{a_1}{a_0}$$ and $${b_2}{b_1}{b_0}$$ and $$c,$$ the carry in the function that represents the carry generate function when these two numbers are added is
A
$$\eqalign{ & {a_2}{b_2} + {a_2}{a_1}{b_1} + {a_2}{a_1}{a_0}{b_0} + {a_2}{a_0}{b_1}{b_2}{b_1} \cr & + {a_1}{a_0}{b_2}{b_0} + {a_0}{b_2}{b_1}{b_0} \cr} $$
B
$$\eqalign{ & {a_2}{b_2} + {a_2}{b_1}{b_0} + {a_2}{a_1}{b_1}{b_0} + {a_1}{a_0}{b_2}{b_1} + {a_1}{a_0}{b_2} \cr & + {a_1}{a_0}{b_2}{b_0} + {a_2}{b_0}{b_1}{b_0} \cr} $$
C
$${a_2} + {b_2} + \left( {{a_2} \oplus {b_2}} \right)\left( {{a_1} + {b_1} + \left( {{a_1} \oplus {b_1}} \right)\left( {{a_0} + {b_0}} \right)} \right)$$
D
$$\eqalign{ & {a_2}{b_2} + \overline {{a_2}} {a_1}{b_1} + \overline {{a_2}{a_1}} {a_0}{b_0} + \cr & {a_2}{a_0}\overline {{b_1}} {b_0} + {a_1}\overline {{b_2}} {b_1} + \overline {{a_1}} {a_0}\overline {{b_2}} {b_0} + {a_0}\overline {{b_2}{b_1}} {b_0} \cr} $$
2
GATE CSE 2005
MCQ (Single Correct Answer)
+2
-0.6
The data given below. Solve the problems and choose the correct answer. GATE CSE 2005 Computer Organization - Computer Arithmetic Question 4 English

Mantissa is a pure fraction in sign - magnitude form. The decimal number $$0.239 \times {2^{13}}$$ has the following hexadecimal representation without normalization and rounding off

A
$$0D\,\,24$$
B
$$0D\,\,4D$$
C
$$4D\,\,0D$$
D
$$4D\,\,3$$
3
GATE CSE 2005
MCQ (Single Correct Answer)
+2
-0.6
The data given below. Solve the problems and choose the correct answer. GATE CSE 2005 Computer Organization - Computer Arithmetic Question 3 English

The normalized representation for the above format is specified as follows. The mantissa has an implicit preceding the binary (radix) point. Assume that only $$0's$$ are padded in while shifting a field. The normalized representation of the above $$\left( {0.239 \times {2^{13}}} \right)$$ is

A
$$0A$$ $$20$$
B
$$11$$ $$34$$
C
$$4D$$ $$D0$$
D
$$4A$$ $$E8$$
4
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
$$A$$ $$4$$-bit carry look ahead adder, which adds two $$4$$-bit numbers, is designed using $$AND,$$ $$OR,$$ $$NOT,$$ $$NAND,$$ $$NOR$$ gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level $$AND$$-$$OR$$ logic.
A
$$4$$ times units
B
$$6$$ time units
C
$$10$$ time units
D
$$12$$ time units
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