A sample-and-hold $$(S/H)$$ circuit, having a holding capacitor of $$0.1$$ $$nF,$$ is used at the input of an $$ADC$$ (analog-to-digital converter). The conversion time of the $$ADC$$ is $$1\,\,\mu \sec ,$$ and during this time, the capacitor should not lose more than $$0.5\% $$ of the charge put across it during the sampling time. The maximum value of the input signal to the $$S/H$$ circuit is $$5V.$$ The leakage current of the $$S/H$$ circuit should be less than

In an $$RC$$- coupled common Emitter amplifier which of the following is true?