A $$10{\raise0.5ex\hbox{$\scriptstyle 1$} \kern-0.1em/\kern-0.15em \lower0.25ex\hbox{$\scriptstyle 2$}}$$ digit timer counter possesses a base clock of frequency $$100$$ $$MHz$$. When measuring a particular input, the reading obtained is the same in: (i) Frequency mode of operation with a gating time of one second and (ii) Period mode of operation (in the $$ \times \,\,\,10$$ ns scale). The frequency of the unknown input (reading obtained) in $$Hz$$ is _______.

A $$4\,{1 \over 2}$$ digit $$DMM$$ has the error specification as $$0.2$$% of reading $$+10$$ counts. If a dc voltage of $$100$$ $$v$$ is read on its $$200$$ $$V$$ full scale. The maximum error that can be expressed in the reading is _______.

The simplified block diagram of a $$10$$bit A/D converter of dual slope integrator type is shown in fig. The $$10$$-bit counter at the output is clocked by a $$1MHz$$ clock. Assuming negligible timing overhead for the control logic, the maximum frequency of the analog signal that can be converted using this A/D converter is approximately.

For a dual $$ADC$$ type $$3\,\,{1 \over 2}$$ digit $$DVM$$, the reference voltage is $$100mV$$ and the first integration time is set to $$300$$$$ms$$. For some input voltage, the ''deintegration'' period is $$370.2ms$$. The $$DVM$$ will indicate