1
GATE EE 2017 Set 2
Numerical
+2
-0
A $$10{\raise0.5ex\hbox{\scriptstyle 1} \kern-0.1em/\kern-0.15em \lower0.25ex\hbox{\scriptstyle 2}}$$ digit timer counter possesses a base clock of frequency $$100$$ $$MHz$$. When measuring a particular input, the reading obtained is the same in: (i) Frequency mode of operation with a gating time of one second and (ii) Period mode of operation (in the $$\times \,\,\,10$$ ns scale). The frequency of the unknown input (reading obtained) in $$Hz$$ is _______.
2
GATE EE 2011
+2
-0.6
A $$4\,{1 \over 2}$$ digit $$DMM$$ has the error specification as $$0.2$$% of reading $$+10$$ counts. If a dc voltage of $$100$$ $$v$$ is read on its $$200$$ $$V$$ full scale. The maximum error that can be expressed in the reading is _______.
A
$$\pm \,\,0.1\%$$
B
$$\pm \,\,0.2\%$$
C
$$\pm \,\,0.3\%$$
D
$$\pm \,\,0.4\%$$
3
GATE EE 2003
+2
-0.6
The simplified block diagram of a $$10$$bit A/D converter of dual slope integrator type is shown in fig. The $$10$$-bit counter at the output is clocked by a $$1MHz$$ clock. Assuming negligible timing overhead for the control logic, the maximum frequency of the analog signal that can be converted using this A/D converter is approximately.
A
$$2$$ $$kHz$$
B
$$1$$ $$kHz$$
C
$$500Hz$$
D
$$250Hz$$
4
GATE EE 1999
+2
-0.6
For a dual $$ADC$$ type $$3\,\,{1 \over 2}$$ digit $$DVM$$, the reference voltage is $$100mV$$ and the first integration time is set to $$300$$$$ms$$. For some input voltage, the ''deintegration'' period is $$370.2ms$$. The $$DVM$$ will indicate
A
$$123.4$$
B
$$199.9$$
C
$$100.0$$
D
$$1.414$$
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