1

### AIPMT 2003

Reverse bias applied to a junction diode
A
lowers the potential barrier
B
raises the potential barrier
C
increases the majority carrier current
D
increases the minority carrier current

## Explanation

In reverse bias, the size of the depletion region increases thereby increasing the potential barrier.
2

### AIPMT 2002

For the given circuit of p-n junction diode which is correct A
in forward bias the voltage across R is V
B
in reverse bias the voltage across R is V
C
in forward bias the voltage across R is 2V
D
in reverse bias the voltage across R is 2V.

## Explanation

In forward biasing, the resistance of p-n junction diode is very low to the flow of current. So practically all the voltage will be dropped across the resistance R, i.e. voltage across R will be V.

In reverse biasing, the resistance of p-n junction diode is very high. So the voltage drop across R is zero.
3

### AIPMT 2002

The given truth table is for which logic gate

$\matrix{ A & B & Y \cr 1 & 1 & 0 \cr 0 & 1 & 1 \cr 1 & 0 & 1 \cr 0 & 0 & 1 \cr }$
A
NAND
B
XOR
C
NOR
D
OR.

## Explanation

This truth table represents NAND gate. 4

### AIPMT 2002

In a p-n junction
A
high potential at n side and low potential at p side
B
high potential at P side and low potential at n side
C
p and n both are at same potential
D
undetermined.

## Explanation

For conduction, p-n junction must be forward biased. For this p-side should be connected to higher potential and n-side to lower potential.