1
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
The microinstructions stored in the control memory of a processor have a width of $$26$$ bits. Each microinstruction is divided into three fields: a micro-operation of $$13$$ bits, a next address field $$(X),$$ and a $$MUX$$ select field $$(Y).$$ There are $$8$$ status bits in the inputs of the $$MUX$$.
How many bits are there in the $$X$$ and $$Y$$ fields, and what is the size of the control memory in number of words?
2
GATE CSE 2002
MCQ (Single Correct Answer)
+2
-0.6
Horizontal micro programming
3
GATE CSE 2001
MCQ (Single Correct Answer)
+2
-0.6
Arrange the following configuration for CPU in decreasing order of operating speeds: Hardwired control, vertical micro- programming, horizontal micro-programming
4
GATE CSE 2001
MCQ (Single Correct Answer)
+2
-0.6
Consider the following datapath of a simple non-pipelined $$CPU.$$ The registers $$A,B,$$ $${A_1},{A_2},$$ $$MDR,$$ the bus and the $$ALU$$ are $$8$$-bit wide. $$SP$$ and $$MAR$$ are $$16$$-bit registers. The $$MUX$$ is of size $$8 \times \left( {2:1} \right)$$ and the $$DEMUX$$ is of size $$8 \times \left( {1:2} \right)$$. Each memory operation takes $$2$$ $$CPU$$ clock cycles and uses $$MAR$$ (Memory Address Register) and $$MDR$$ (Memory Data register). $$SP$$ can be decremented locally.
The $$CPU$$ instruction $$''push$$ $$r'',$$ where $$r=A$$ or $$B,$$ has the specification
$$\eqalign{
& \,\,\,\,\,\,\,\,\,\,\,\,\,M\left[ {SP} \right] \leftarrow r \cr
& \,\,\,\,\,\,\,\,\,\,\,\,\,SP \leftarrow SP - 1 \cr} $$
How many $$CPU$$ clock cycles are needed to execute the $$''push$$ $$r''$$ instruction?
Questions Asked from Alu Data Path and Control Unit (Marks 2)
Number in Brackets after Paper Indicates No. of Questions
GATE CSE Subjects
Theory of Computation
Operating Systems
Algorithms
Database Management System
Data Structures
Computer Networks
Software Engineering
Compiler Design
Web Technologies
General Aptitude
Discrete Mathematics
Programming Languages