1
GATE CSE 2013
MCQ (Single Correct Answer)
+2
-0.6
Consider the following sequence of micro-operations
$$\eqalign{ & \,\,\,\,\,\,\,\,\,\,\,\,\,MBR\,\,\,\,\,\,\, \leftarrow PC \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,MAR\,\,\,\,\,\,\, \leftarrow X \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,PC\,\,\,\,\,\,\,\,\,\,\,\, \leftarrow Y \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,Memory\, \leftarrow MBR \cr} $$

Which one of the following is a possible operation performed by this sequence?

A
Instruction fetch
B
Operand fetch
C
Conditional branch
D
Initiation of interrupt service
2
GATE CSE 2005
MCQ (Single Correct Answer)
+2
-0.6
Consider the following data path of a $$CPU$$ GATE CSE 2005 Computer Organization - Alu Data Path and Control Unit Question 4 English

The, $$ALU$$, the bus and all the registers in the data path are of identical size. All operations including incrementation of the $$PC$$ and the $$GPRs$$ are to be carried out in the $$ALU.$$ Two clock cycle are needed for memory read operation-the first one for loading address in the $$MAR$$ and the next one for loading data from the memory but into the $$MDR.$$

The instruction $$''add$$ $$R0$$, $$R1''$$ has the register transfer interpretation $$R0 < = R0 + R1.$$ The minimum number of cycles needed for execution cycle of this instruction is

A
$$2$$
B
$$3$$
C
$$4$$
D
$$5$$
3
GATE CSE 2005
MCQ (Single Correct Answer)
+2
-0.6
Consider the following data path of a $$CPU$$ GATE CSE 2005 Computer Organization - Alu Data Path and Control Unit Question 3 English

The, $$ALU$$, the bus and all the registers in the data path are of identical size. All operations including incrementation of the $$PC$$ and the $$GPRs$$ are to be carried out in the $$ALU.$$ Two clock cycle are needed for memory read operation-the first one for loading address in the $$MAR$$ and the next one for loading data from the memory but into the $$MDR.$$

The instruction $$''call$$ $$Rn,sub''$$ is a two word instruction. Assuming that $$PC$$ is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is $$$\eqalign{ & Rn < = PC + 1; \cr & PC < = M\left[ {PC} \right]; \cr} $$$
The minimum number of $$CPU$$ clock cycles needed during the execution cycle of this instruction is :

A
$$2$$
B
$$3$$
C
$$4$$
D
$$5$$
4
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
The microinstructions stored in the control memory of a processor have a width of $$26$$ bits. Each microinstruction is divided into three fields: a micro-operation of $$13$$ bits, a next address field $$(X),$$ and a $$MUX$$ select field $$(Y).$$ There are $$8$$ status bits in the inputs of the $$MUX$$. GATE CSE 2004 Computer Organization - Alu Data Path and Control Unit Question 5 English

How many bits are there in the $$X$$ and $$Y$$ fields, and what is the size of the control memory in number of words?

A
$$10,3, 1024$$
B
$$8, 5, 256$$
C
$$5, 8. 2048$$
D
$$10, 3, 512$$
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