1
GATE EE 2003
+2
-0.6
The Boolean expression $$X\overline Y Z + XYZ + \overline X Y\overline Z + \overline X \overline Y Z + XY\overline Z$$ can be simplified to
A
$$X\overline Z + \overline X Z + YZ$$
B
$$XZ + \overline Y Z + Y\overline Z$$
C
$$\overline X Z + YZ + XZ$$
D
$$\overline X \overline Y + Y\overline Z + \overline X Z$$
2
GATE EE 2003
+1
-0.3
Figure shows a $$4$$ to $$1$$ $$MUX$$ to be used to implement the sum $$S$$ of a $$1$$-bit full adder with input bits $$P$$ and $$Q$$ and the carry input $${C_{in}}.$$ Which of the following combinations of inputs to $${{\rm I}_0},\,\,{{\rm I}_1},\,\,{{\rm I}_2}$$ and $$\,\,{{\rm I}_3}$$ of the $$MUX$$ will realize the sum $$S$$?
A
$${{\rm I}_0} = {{\rm I}_1} = {C_{in}};\,{{\rm I}_2} = {{\rm I}_3} = {\overline C _{in}}$$
B
$${{\rm I}_0} = {{\rm I}_1} = {\overline C _{in}};\,{{\rm I}_2} = {{\rm I}_3} = {C_{in}}$$
C
$${{\rm I}_0} = {{\rm I}_3} = {\overline C _{in}};\,{{\rm I}_1} = {{\rm I}_2} = {\overline C _{in}}$$
D
$${{\rm I}_0} = {{\rm I}_3} = {\overline C _{in}};\,{{\rm I}_1} = {{\rm I}_2} = {C_{in}}$$
3
GATE EE 2003
+2
-0.6
The shift register shown in Fig. is initially loaded with the bit pattern $$1010.$$ Subsequently the shift register is clocked, and with each clock pulse the pattern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the left most position $$(MSB).$$ After how many clock pulses will the content of the shift register become $$1010$$ again?
A
$$3$$
B
$$7$$
C
$$11$$
D
$$15$$
4
GATE EE 2003
+2
-0.6
The simplified block diagram of a $$10$$-bit $$A/D$$ converter of dual slope integrator type is shown in Fig. The $$10$$-bit counter at the output is clocked by a $$1$$ $$MHz$$ clock. Assuming negligible timing overhead for the control logic, the maximum frequency of the analog signal that can be converted using this $$A/D$$ converter is approximately. Input sample to be converter
A
$$2$$ $$kHz$$
B
$$1$$ $$kHz$$
C
$$500$$ $$Hz$$
D
$$250$$ $$Hz$$
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