The shift register shown in Fig. is initially loaded with the bit pattern $$1010.$$ Subsequently the shift register is clocked, and with each clock pulse the pattern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the left most position $$(MSB).$$ After how many clock pulses will the content of the shift register become $$1010$$ again?

The simplified block diagram of a $$10$$-bit $$A/D$$ converter of dual slope integrator type is shown in Fig. The $$10$$-bit counter at the output is clocked by a $$1$$ $$MHz$$ clock. Assuming negligible timing overhead for the control logic, the maximum frequency of the analog signal that can be converted using this $$A/D$$ converter is approximately. Input sample to be converter

The following program is written for an $$8085$$ microprocessor to add two bytes located at memory addresses $$1FFE$$ and $$1FFF$$
$$\eqalign{ & LXI\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,H,\,\,\,1FFE \cr & MOV\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,B,\,\,\,M \cr & INR\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,L \cr & MOV\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,A,\,\,\,M \cr & ADD\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,B \cr & INR\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,L \cr & MOV\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,M,\,\,\,A \cr & XRA\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,A \cr} $$

On completion of the execution of the program, the result of additional is found.

A segment of a circuit is shown in figure. $${v_R} = 5\,\,V,\,\,{v_C} = 4\sin 2t.$$ The voltage $${V_L}$$ is given by