1
GATE EE 2003
MCQ (Single Correct Answer)
+2
-0.6
The block diagram of a control system is shown in Fig. The transfer function $$G(s) = Y(s)/U(s)$$ of the system is GATE EE 2003 Control Systems - Block Diagram and Signal Flow Graph Question 10 English
A
$${1 \over {18\left( {1 + {s \over {12}}} \right)\left( {1 + {s \over 3}} \right)}}$$
B
$${1 \over {27\left( {1 + {s \over 6}} \right)\left( {1 + {s \over 9}} \right)}}$$
C
$${1 \over {27\left( {1 + {s \over {12}}} \right)\left( {1 + {s \over 9}} \right)}}$$
D
$${1 \over {27\left( {1 + {s \over 9}} \right)\left( {1 + {s \over 3}} \right)}}$$
2
GATE EE 2003
MCQ (Single Correct Answer)
+2
-0.6
The following program is written for an $$8085$$ microprocessor to add two bytes located at memory addresses $$1FFE$$ and $$1FFF$$
$$\eqalign{ & LXI\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,H,\,\,\,1FFE \cr & MOV\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,B,\,\,\,M \cr & INR\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,L \cr & MOV\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,A,\,\,\,M \cr & ADD\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,B \cr & INR\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,L \cr & MOV\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,M,\,\,\,A \cr & XRA\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,A \cr} $$

On completion of the execution of the program, the result of additional is found.

A
in the register $$A$$
B
at the memory address $$1000$$
C
at the memory address $$1F00$$
D
at the memory address $$2000$$
3
GATE EE 2003
MCQ (Single Correct Answer)
+2
-0.6
The simplified block diagram of a $$10$$-bit $$A/D$$ converter of dual slope integrator type is shown in Fig. The $$10$$-bit counter at the output is clocked by a $$1$$ $$MHz$$ clock. Assuming negligible timing overhead for the control logic, the maximum frequency of the analog signal that can be converted using this $$A/D$$ converter is approximately. Input sample to be converter GATE EE 2003 Digital Electronics - Analog to Digital and Digital to Analog Converter Question 6 English
A
$$2$$ $$kHz$$
B
$$1$$ $$kHz$$
C
$$500$$ $$Hz$$
D
$$250$$ $$Hz$$
4
GATE EE 2003
MCQ (Single Correct Answer)
+2
-0.6
The shift register shown in Fig. is initially loaded with the bit pattern $$1010.$$ Subsequently the shift register is clocked, and with each clock pulse the pattern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the left most position $$(MSB).$$ After how many clock pulses will the content of the shift register become $$1010$$ again? GATE EE 2003 Digital Electronics - Sequential Circuits Question 18 English
A
$$3$$
B
$$7$$
C
$$11$$
D
$$15$$
EXAM MAP
Medical
NEETAIIMS
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
Civil Services
UPSC Civil Service
Defence
NDA
Staff Selection Commission
SSC CGL Tier I
CBSE
Class 12