Select the correct statement(s) regarding CMOS implementation of NOT gates.

for the circuit shown, the clock frequency is f₀ and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, ___________.

A state transition diagram with states A, B, and C, and transition probabilities p₁, p₂, ....., p₇ is shown in the figure (e.g., p₁ denotes the probability of transition from state A to B). For this state diagram, select the statements which is/are universally true.

Consider a Boolean gate (D) where the output Y is related to the inputs A and b as, Y = A + $$\overline B $$, where + denotes logical OR operation. The Boolean inputs '0' and '1' are also available separately. Using instances of only D gates and inputs '0' and '1', ___________ (select the correct options).