(a) NM_L = V_IL $$-$$ V_OL

NM_H = V_OH $$-$$ V_IH

when, V_TN = | V_TP |

and K_n = K_p

V_IT = $${{{V_{DD}}} \over 2}$$ and NM_L = NM_H

when $$ \uparrow {{{K_p}} \over {{K_n}}}$$ > 1, V_IL $$\uparrow$$, V_IH $$\uparrow$$

NM_H $$\downarrow$$ and NM_L $$\uparrow$$

When, $$ \downarrow {{{K_p}} \over {{K_n}}}$$ < 1, V_IL $$\downarrow$$, V_IH $$\uparrow$$

NM_H $$\uparrow$$ and NM_L $$\uparrow$$

i.e. NM_L and NM_H depends on transistor sizing and they are equal for certain condition only.

(b) Dynamic power consumption during switching is non-zero due to capacitive loading of next state.

(c) For $$\matrix{ {\mathop {{V_{DD}} - \left| {{V_{TP}}} \right| \le {V_{in}} \le {V_{DD}}}\limits_{(logic\,high\,input)} \Rightarrow } & {PMOS \to Cut - off} \cr {} & {NMOS \to \,Linear} \cr } $$

(d) Switching speed depends on charging and discharging of load capacitor for pull up and pull down of output voltage respectively.

Fast charging and discharging of capacitor depends on mobility of charge carrier.

$$\tau$$_charging = R_PMOS C_L (to bring o/p at logic high)

$$\tau$$_discharging = R_NMOS C_L (to bring o/p at logic low)

and also propagation delay,

$${\tau _p} = {{{\tau _{PLH}} + {\tau _{PHL}}} \over 2}$$

where, $${T_{PLH}} = {{{C_L}\,{V_{DD}}} \over {{\mu _p}{C_{ox}}\left( {{W \over L}} \right){{({V_{GS}} - {V_{Tp}})}^2}}}$$

$${T_{PHL}} = {{{C_L}\,{V_{DD}}} \over {{\mu _p}{C_{ox}}\left( {{W \over L}} \right){{({V_{GS}} - {V_{TN}})}^2}}}$$

Using average charge model.

Hence, (c) is only correct statement.