1
GATE CSE 2018
MCQ (Single Correct Answer)
+2
-0.6
The following are some events that occur after a device controller issues an interrupt while process $$L$$ is under execution.

$$(P)$$ The processor pushes the process status of $$L$$ onto the control stack.
$$(Q)$$ The processor finishes the execution of the current instruction.
$$(R)$$ The processor executes the interrupt service routine.
$$(S)$$ The processor pops the process status of $$L$$ from the control stack.
$$(T)$$ The processor loads the new PC value based on the interrupt.

Which one of the following is the correct order in which the events above occur?

A
$$QPTRS$$
B
$$PTRSQ$$
C
$$TRPQS$$
D
$$QTPRS$$
2
GATE CSE 2011
MCQ (Single Correct Answer)
+2
-0.6
On a non-pipe-lined sequential processor, a program segment, which is a part of the interrrupt service routine, is given to transfer $$500$$ bytes from an $${\rm I}/O$$ device to memory. Initialize the address register Initialize the count to $$500$$
$$LOOP:$$ Load a byte from device Store in memory at address given by address register $$$\eqalign{ & Increment\,\,\,the\,\,\,address\,\,register \cr & Decrement\,\,\,the\,\,count \cr & If\,\,\,count!\,\,\, = 0\,\,\,go\,\,\,to\,\,\,LOOP \cr} $$$

Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is non- load/store instruction. The load-store instructions take two clock cycles to execute.

The designer of the system also has an alternate approach of using the $$DMA$$ controller to implement the same transfer. The $$DMA$$ controller requires $$20$$ clock cycles for initialization and other overheads. Each $$DMA$$ transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.

What is the approximate speed up when the $$DMA$$ controller based design is used in place of the interrupt driven program based input-output?

A
$$3.4$$
B
$$4.4$$
C
$$5.1$$
D
$$6.7$$
3
GATE CSE 2005
MCQ (Single Correct Answer)
+2
-0.6
A device with data transfer rate $$10$$ $$KB/sec$$ is connected to a $$CPU.$$ Data is transferred byte-wise. Let the interrupt overhead be $$4$$ $$\mu \sec $$. The byte transfer time between the device interface register and $$CPU$$ or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program controlIed mode?
A
$$15$$
B
$$25$$
C
$$35$$
D
$$45$$
4
GATE CSE 2005
MCQ (Single Correct Answer)
+2
-0.6
Consider the disk drive with the following specifications $$16$$ surfaces, $$512$$ tracks/surface, $$512$$ sectors/track, $$1$$ $$KB/sector$$, rotation speed $$3000$$ $$rpm.$$ The disk is operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a $$4$$ byte word from the memory in each $$DMA$$ cycle. Memory cycle time is $$40$$ $$nsec$$. The maximum percentage of time that the $$CPU$$ gets blocked during $$DMA$$ operation is
A
$$10$$
B
$$25$$
C
$$40$$
D
$$50$$
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