1
GATE CSE 1999
Subjective
+5
-0
An instruction pipeline consists of $$4$$ stages: Fetch (F), Decode field (D), Execute (E), and Result-Write (W). The $$5$$ instructions in a certain instruction sequence need these stages for the different number of clock cycles as shown by the table
below.
Find the number of clock cycles needed to perform the $$5$$ instructions
Questions Asked from Pipelining (Marks 5)
Number in Brackets after Paper Indicates No. of Questions
GATE CSE Subjects
Discrete Mathematics
Programming Languages
Theory of Computation
Operating Systems
Computer Organization
Database Management System
Data Structures
Computer Networks
Algorithms
Compiler Design
Software Engineering
Web Technologies
General Aptitude