The figure below shows a multiplexer where $S_1$ and $S_0$ are the select lines, $I_0$ to $I_3$ are the input data lines, $E N$ is the enable line, and $F(P, Q, R)$ is the output. $F$ is

A 10 bit D/A converter is calibrated over the full range 0 to 10 V . If the input to the D/A converter is 13 A (in hex), the output (rounded off to three decimal places) is $\_\_\_\_$ V.

For the components in the sequential circuit shown below, $t_{p d}$ is the propagation delay, $t_{\text {secup }}$ is the setup time and $t_{\text {hold }}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is $\_\_\_\_$ MHz.

$P, Q$ and $R$ are the decimal integers corresponding to the 4-bit binary number 1100 considered in signed magnitude, 1 's complement and 2 's complement representation, respectively. The 6 -bit 2 's complement representation of ( $P+Q+R$ ) is