For the components in the sequential circuit shown below, $t_{p d}$ is the propagation delay, $t_{\text {secup }}$ is the setup time and $t_{\text {hold }}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is $\_\_\_\_$ MHz.

$P, Q$ and $R$ are the decimal integers corresponding to the 4-bit binary number 1100 considered in signed magnitude, 1 's complement and 2 's complement representation, respectively. The 6 -bit 2 's complement representation of ( $P+Q+R$ ) is

The state diagram of a sequence detector is shown below. State $S_0$ is the initial state of the sequence detector. If the output is 1 , then

A transmission line of length $3 \lambda / 4$ and having a characteristic impedance of $50 \Omega$ is terminated with a load of $400 \Omega$. The impedance (rounded off to two decimal places) seen at the input end of the transmission line is $\_\_\_\_$ $\Omega$.