The channel resistance of an N-channel JFET shown in the figure below is 600 W when the full channel thickness (t_ch) of 10 μm is available for conduction. The built-in voltage of the gate P⁺N junction (V_bi) is -1 V. When the gate to source voltage (V_GS) is 0 V, the channel is depleted by 1 μm on each side due to the built in voltage and hence the thickness available for conduction is only 8 μm The channel resistance when V_GS = -3 V is

The channel resistance of an N-channel JFET shown in the figure below is 600 W when the full channel thickness (t_ch) of 10 μm is available for conduction. The built-in voltage of the gate P⁺N junction (V_bi) is -1 V. When the gate to source voltage (V_GS) is 0 V, the channel is depleted by 1 μm on each side due to the built in voltage and hence the thickness available for conduction is only 8 μm The channel resistance when V_GS = 0 V is

In the circuit shown below, for the MOS transistors, $$\mu_nC_{ox}\;=\;100\;\mu A/V^2$$ and the threshold voltage V_T = 1 V. The voltage V_x at the source of the upper transistor is

The system of equations $$x+y+z=6,$$ $$x+4y+6z=20,$$ $$x + 4y + \lambda z = \mu $$ has no solution for values of $$\lambda $$ and $$\mu $$ given by