1
GATE ECE 2025
Numerical
+1
-0
A 4-bit weighted-resistor DAC with inputs $b_3, b_2, b_1$, and $b_0$ (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when the corresponding input bits are logic ' 1 ' and open otherwise. When the input $b_3 b_2 b_1 b_0$ changes from 1110 to 1101, the magnitude of the change in the output voltage $V_O$ (in mV , rounded off to the nearest integer) is ____________. GATE ECE 2025 Digital Circuits - Analog to Digital and Digital to Analog Converters Question 1 English
Your input ____
2
GATE ECE 2025
MCQ (Single Correct Answer)
+2
-0.67
A 10-bit analog-to-digital converter (ADC) has a sampling frequency of 1 MHz and a full scale voltage of 3.3 V . For an input sinusoidal signal with frequency 500 kHz , the maximum SNR (in dB, rounded off to two decimal places) and the data rate (in Mbps) at the output of the ADC are _________ , respectively.
A
61.96 and 10
B
61.96 and 5
C
33.36 and 10
D
33.36 and 5
3
GATE ECE 2025
MCQ (Single Correct Answer)
+2
-0.67

A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input $P 0$ is set to logic ' 0 ' and $P 1$ is set to logic ' 1 ' at all times. The timing diagram of the inputs SEL and $S$ are also shown below.

The sequence of output $Y$ from time $T_0$ to $T_3$ is $\qquad$ .

GATE ECE 2025 Digital Circuits - Sequential Circuits Question 1 English
A
1011
B
0100
C
0010
D
1101
4
GATE ECE 2025
Numerical
+2
-0

In the circuit shown below, the AND gate has a propagation delay of 1 ns . The edgetriggered flip-flops have a set-up time of 2 ns , a hold-time of 0 ns , and a clock-to-Q delay of 2 ns .

The maximum clock frequency (in MHz , rounded off to the nearest integer) such that there are no setup violations is___________ .

GATE ECE 2025 Digital Circuits - Sequential Circuits Question 2 English
Your input ____
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