Consider a system where $x_1(t), x_2(t)$, and $x_3(t)$ are three internal state signals and $u(t)$ is the input signal. The differential equations governing the system are given by

$$ \frac{d}{d t}\left[\begin{array}{l} x_1(t) \\ x_2(t) \\ x_3(t) \end{array}\right]=\left[\begin{array}{ccc} 2 & 0 & 0 \\ 0 & -2 & 0 \\ 0 & 0 & 0 \end{array}\right]\left[\begin{array}{l} x_1(t) \\ x_2(t) \\ x_3(t) \end{array}\right]+\left[\begin{array}{l} 1 \\ 1 \\ 1 \end{array}\right] u(t) $$

Which of the following statements is/are TRUE?

Consider a system represented by the block diagram shown below. Which of the following signal flow graphs represent(s) this system? Choose the correct option(s).

A 3-input majority logic gate has inputs $X, Y$ and $Z$. The output $F$ of the gate is logic ' 1 ' if two or more of the inputs are logic ' 1 '. The output $F$ is logic ' 0 ' if two or more of the inputs are logic '0'. Which one of the following options is a Boolean expression of the output $F$ ?

A full adder and an XOR gate are used to design a digital circuit with inputs $X, Y$, and $Z$, and output $F$, as shown below. The input $Z$ is connected to the carry-in input of the full adder.

If the input $Z$ is set to logic ' 1 ', then the circuit functions as __________ with $X$ and $Y$ as inputs.