A 10-bit analog-to-digital converter (ADC) has a sampling frequency of 1 MHz and a full scale voltage of 3.3 V . For an input sinusoidal signal with frequency 500 kHz , the maximum SNR (in dB, rounded off to two decimal places) and the data rate (in Mbps) at the output of the ADC are _________ , respectively.

A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input $P 0$ is set to logic ' 0 ' and $P 1$ is set to logic ' 1 ' at all times. The timing diagram of the inputs SEL and $S$ are also shown below.

The sequence of output $Y$ from time $T_0$ to $T_3$ is $\qquad$ .

In the circuit shown below, the AND gate has a propagation delay of 1 ns . The edgetriggered flip-flops have a set-up time of 2 ns , a hold-time of 0 ns , and a clock-to-Q delay of 2 ns .

The maximum clock frequency (in MHz , rounded off to the nearest integer) such that there are no setup violations is___________ .

A square metal sheet of $4 \mathrm{~m} \times 4 \mathrm{~m}$ is placed on the $x-y$ plane as shown in the figure below. If the surface charge density (in $\mu \mathrm{C} / \mathrm{m}^2$ ) on the sheet is $\rho_s(x, y)=4|y|$, then the total charge (in $\mu \mathrm{C}$, rounded off to the nearest integer) on the sheet is___________ .