1
GATE ECE 2018
MCQ (Single Correct Answer)
+1
-0.33
The Nyquist stability criterion and the Routh criterion both are powerful analysis tools for determining the stability of feedback controllers. Identify which of the following statements is FALSE.
A
The closed-loop frequency response for a unity feedback system cannot be obtained from the Nyquist plot.
B
The Routh criterion is not applicable in the condition of transport lag, which can be readily handled by the Nyquist criterion.
C
The general shape of the Nyquist plot is readily obtained from the Bode magnitude plot for all minimum-phase systems.
D
Both the criteria provide information relative to the stable gain range of the system.
2
GATE ECE 2018
Numerical
+2
-0
The figure below shows the Bode magnitude and phase plots of a stable transfer function

$$G(s) = {{{n_0}} \over {{s^3} + {d_2}{s^2} + {d_1}s + {d_0}}}$$. GATE ECE 2018 Control Systems - Frequency Response Analysis Question 8 English

Consider the negative unity feedback configuration with gain k in the feedforward path. The closed loop is stable for k < k0. The maximum value of k0 is ______.
Your input ____
3
GATE ECE 2018
Numerical
+1
-0
A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds and the RED is turned on for 75 seconds. This traffic light has to be implemented using a finite state machine (FSM). The only input to this FSM is a clock of 5 second period. The minimum number of flip-flops required to implement this FSM is _______.
Your input ____
4
GATE ECE 2018
Numerical
+2
-0
In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data Din using clock CK. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of $${{\Delta T} \over {{T_{CK}}}}$$ = 0.15, where the parameters $$\Delta T$$ and TCK are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal. GATE ECE 2018 Digital Circuits - Sequential Circuits Question 14 English

If the probability of input data bit (Din) transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node X, is _______.
Your input ____