In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data D_in using clock CK. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of $${{\Delta T} \over {{T_{CK}}}}$$ = 0.15, where the parameters $$\Delta T$$ and T_CK are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.

If the probability of input data bit (D_in) transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node X, is _______.

A 2 $$ \times $$ 2 ROM array is built with the help of diodes as shown in the circuit below. Here W₀ and W₁ are signals that select the word lines and B₀ and B₁ are signals that are output of the sense amps based on the stored data corresponding to the bit lines during the read operation.
During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation shown in the circuit diagram above, what are the bits corresponding to D_ij (where i = 0 or 1 and j = 0 or 1) stored in the ROM?

A four-variable Boolean function is realized using 4 $$ \times $$ 1 multiplexers as shown in the figure.
The minimized expression for F(U, V, W, X) is

A function F(A, B, C) defined by three Boolean variables A, B and C when expressed as sum of products is given by

F = $$\overline A .\overline B .\overline C + \overline A .B.\overline C + A.\overline B .\overline C $$

where, $$\overline A $$, $$\overline B $$, and $$\overline C $$ are the complements of the respective variables. The product of sums (POS) form of the function F is