In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input
data Din using clock CK. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for
logic LOW levels. The data bit and clock periods are equal and the value of $${{\Delta T} \over {{T_{CK}}}}$$ = 0.15,
where the parameters $$\Delta T$$ and TCK are shown in the figure. Assume that the Flip-Flop and the
XOR gate are ideal.
If the probability of input data bit (Din) transition in each clock period is 0.3, the average
value (in volts, accurate to two decimal places) of the voltage at node X, is _______.
Your input ____
2
GATE ECE 2018
Numerical
+1
-0
Taylor series expansion of $$f\left( x \right) = \int\limits_0^x {{e^{ - \left( {{{{t^2}} \over 2}} \right)}}} dt$$ around 𝑥 = 0 has the form
f(x) = $${a_0} + {a_1}x + {a_2}{x^2} + ...$$
The coefficient $${a_2}$$ (correct to two decimal places) is equal to _______.
Your input ____
3
GATE ECE 2018
Numerical
+2
-0
The position of a particle y(t) is described by the differential equation :