A function F(A, B, C) defined by three Boolean variables A, B and C when expressed as sum
of products is given by
F = $$\overline A .\overline B .\overline C + \overline A .B.\overline C + A.\overline B .\overline C $$
where, $$\overline A $$, $$\overline B $$, and $$\overline C $$ are the complements of the respective variables. The product of sums
(POS) form of the function F is
A
F = (A + B + C)(A + $$\overline B $$ + C)($$\overline A $$ + B + C)
B
F = ($$\overline A $$ + $$\overline B $$ + $$\overline C $$)($$\overline A $$ + B + $$\overline C $$)(A + $$\overline B $$ + $$\overline C $$)
C
F = (A + B + $$\overline C $$)(A + $$\overline B $$ + $$\overline C $$)($$\overline A $$ + B + $$\overline C $$)($$\overline A $$ + $$\overline B $$ + C)($$\overline A $$ + $$\overline B $$ + $$\overline C $$)
D
F = ($$\overline A $$ + $$\overline B $$ + C)($$\overline A $$ + B + C)(A + $$\overline B $$ + C)(A + B + $$\overline C $$)(A + B + C)
2
GATE ECE 2018
MCQ (Single Correct Answer)
+2
-0.67
A four-variable Boolean function is realized using
4 $$ \times $$ 1
multiplexers as shown in the
figure.
The minimized expression for F(U, V, W, X)
is
A
$$\left( {UV + \overline U \overline V } \right)\overline W $$
B
$$\left( {UV + \overline U \overline V } \right)\left( {\overline W \overline X + \overline W X} \right)$$
C
$$\left( {U\overline V + \overline U V} \right)\overline W $$
D
$$\left( {U\overline V + \overline U V} \right)\left( {\overline W \overline X + \overline W X} \right)$$
3
GATE ECE 2018
Numerical
+2
-0.67
The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for
LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the
output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are
intentionally shorted to implement “wired logic”. Such shorted nodes will be HIGH only if
the outputs of all the gates whose outputs are shorted are HIGH.
The number of distinct values of X3X2X1X0 (out of the 16 possible values) that give
𝑌 = 1 is _______.
Your input ____
4
GATE ECE 2018
Numerical
+1
-0.33
A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN.
In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for
5 seconds and the RED is turned on for 75 seconds. This traffic light has to be implemented
using a finite state machine (FSM). The only input to this FSM is a clock of 5 second period.
The minimum number of flip-flops required to implement this FSM is _______.
