A four-variable Boolean function is realized using 4 $$ \times $$ 1 multiplexers as shown in the figure.
The minimized expression for F(U, V, W, X) is

The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are intentionally shorted to implement “wired logic”. Such shorted nodes will be HIGH only if the outputs of all the gates whose outputs are shorted are HIGH.


The number of distinct values of X₃X₂X₁X₀ (out of the 16 possible values) that give 𝑌 = 1 is _______.

A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds and the RED is turned on for 75 seconds. This traffic light has to be implemented using a finite state machine (FSM). The only input to this FSM is a clock of 5 second period. The minimum number of flip-flops required to implement this FSM is _______.

In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data D_in using clock CK. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of $${{\Delta T} \over {{T_{CK}}}}$$ = 0.15, where the parameters $$\Delta T$$ and T_CK are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.

If the probability of input data bit (D_in) transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node X, is _______.