1
GATE ECE 2015 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The Boolean expression F(X, Y, Z)= $$\overline X Y\overline Z + X\overline {Y\,} \overline Z + XY\overline Z + XYZ$$ converted into the canonical product of sum (POS)from is
A
$$(x + y + z)(x + y + \overline z )(x + \overline y + \overline z )(\overline x + y + \overline z )$$
B
$$(x + \overline y + z)(\overline x + y + \overline z )(\overline x + \overline y + z)(\overline x + \overline y + z)$$
C
$$(x + y + z)(\overline x + y + \overline z )(x + \overline y + z)(\overline x + \overline y + \overline z )$$
D
$$(x + \overline y + \overline z )(\overline x + y + z)(\overline x + \overline y + z)(x + y + z)$$
2
GATE ECE 2015 Set 1
Numerical
+2
-0
All the logic gates shown in the figure have a propagation delay of 20 ns. Let A = C = 0 and B = 1 until time t = 0. At t = 0, all the inputs flip (i.e., A = C = 1 and B = 0) and remain in that state. For t > 0, output Z = 1 for a duration (in ns) of ______________. GATE ECE 2015 Set 1 Digital Circuits - Logic Gates Question 8 English
Your input ____
3
GATE ECE 2015 Set 1
MCQ (Single Correct Answer)
+2
-0.6
A 3-input majority gate is defined by the logic function M (a,b,c) = ab+bc+ca. Which one of the following gates is represented by the function M$$\left( {\overline {M\left( {a,b,c} \right),} M\left( {a,b,\overline c } \right),c} \right)?$$
A
3-Input NAND gate
B
3-Input XOR gate
C
3-Input NOR gate
D
3-Input XNOR gate
4
GATE ECE 2015 Set 1
Numerical
+1
-0
A 16 Kb (=16,384 bit) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is _______.
Your input ____
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