The output F in the digital logic circuit shown in the figure is

Five JK flip - flops are cascaded to form circuit shown in figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in kHz) of the waveform at Q₃ is ______.

The digital logic shown in the figure satisfies the given state diagram when Q₁ is connected to input A of the XOR gate.

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?

A two - port network has scattering parameters given by $$[S]$$ $$ = \left[ {\matrix{ {{s_{11}}} & {{s_{12}}} \cr {{s_{21}}} & {{s_{22}}} \cr } } \right].$$
If the port - 2 of the two - port is short circuited, the $${{s_{11}}}$$ parameter for the resultant one - port network is