A 12-bit ADC is operating with a 1$$\mu $$ sec clock period and the total conversion time is seen to be 14 $$\mu $$ sec. The ADC must br of the

A 4-bit shift register, which shifts 1 bit to the right at every clock pulse, is intialized to values (1000) for (Q₀Q₁Q₂Q₃). The D input is derived from Q₀, Q₂ and Q₃ through two XOR gates as shown in figure.

(a) Write the 4-bit values (Q₀Q₁Q₂Q₃) after each clock pulse till the pattern (1000) reappears on (Q₀Q₁Q₂Q₃).

(b) To what values should the shift register be intialized so that the pattern (1001) occurs after the first clock pulse?

A state machine is required to cycle through the following sequence of states:

One possible implementation of the state machine is shown figure. Specify what signals should be applied to each of the multiplexer inputs

A lossless transmission line having 50 $$\Omega $$ characteristic impedance and lenght $$\lambda /4$$ is short ciruited at one end and connected to an ideal voltage sourec of 1 V at the other end. The current drawn from the voltage source is