1
GATE ECE 1988
Subjective
+8
-0
For the circuit shown in the figure below, sketch V0 against time. Assume that all flip-flops are reset to zero before the clock is applied. GATE ECE 1988 Digital Circuits - Sequential Circuits Question 7 English
2
GATE ECE 1988
MCQ (Single Correct Answer)
+1
-0.3
The circuit given below is a GATE ECE 1988 Digital Circuits - Sequential Circuits Question 6 English
A
J-K Flip-flop
B
Johnson's counter
C
R-S latch
D
None of above
3
GATE ECE 1988
MCQ (Single Correct Answer)
+2
-0.6
In a good conductor the phase relation between the tangential components of electric field Et and the magnetic field Ht is as follows
A
Et and Ht are in phase
B
Et and Ht are out of phase
C
Ht leads Et by 900
D
Et leads Ht by 450
4
GATE ECE 1988
MCQ (Single Correct Answer)
+2
-0.6
A two - wire transmission line of characteristic impedance $$Z_0$$ is connected to a load of impedance $${Z_L}({Z_L}\, \ne \,\,{Z_0})$$. Impedance matching cannot be achieved with
A
a quarter-wavelength transformer
B
a half-wavelength transformer
C
an open-circuited parallel stub
D
a short-circuited parallel stub
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