Consider a closed-loop system shown in fig. (a) below. The root locus for it is shown in fig. (b). The closed-loop transfer function for the system is

Minimum number of 2-input NAND gates required to implement the function, f=($$\overline X $$+$$\overline Y $$)(Z+W) is

For the circuit shown below the output Fis given by

The minimum number of 2-input NAND gates required to implement the Boolean function Z=A$$\overline {B\,} $$C, assuming that A, B and C are available, is