1
GATE ECE 1988
MCQ (Single Correct Answer)
+1
-0.3
A 8bit $$\mu $$p has 16bit address bus. A 1KB memory chip is interfaced to processor as shown ib figure. The address range for the chip is _____________. GATE ECE 1988 Microprocessors - Pin Details of 8085 and Interfacing with 8085 Question 1 English
A
F000FH - F40EH
B
F100H - F4FFH
C
F000H - F3FFH
D
F700H - FAFFH
2
GATE ECE 1988
MCQ (Single Correct Answer)
+2
-0.6

If an impedance ZL is connected across a voltage source V with source impedance ZS, then for maximum power transfer, the load impedance must be equal to

A
Source impedance ZS
B
Complex conjugate of ZS
C
Real part of ZS
D
Imaginary part of ZS
3
GATE ECE 1988
Subjective
+8
-0
The circuit shown below is initially in a steady state condition. At $$t = 0$$, the switch '$$S$$' is opened.

(i) Determine the initial voltage $${V_c}\left( {{0^ - }} \right)$$ across the capacitor and initial current $${i_L}\left( {{0^ - }} \right)$$ through the inductor.
(ii) Find the voltage $${v_L}\left( t \right)$$ across the inductor for $$t > 0$$.

GATE ECE 1988 Network Theory - Transient Response Question 7 English
4
GATE ECE 1988
MCQ (Single Correct Answer)
+2
-0.6
Two two-port networks are connected in parallel. The combination is to be represented as a single two-port network. The parameters of this network are obtained by addition of the individual
A
z parameters
B
h parameters
C
y parameters
D
ABCD parameters
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