Implement the function $$F=\left(\overline A+\overline B\right)\left(\overline C+\overline D\right)$$ using two open collector TTL 2-input NAND gates.

The circuit shown below uses TTL flip-flops. The flip-flops are triggered at the negative transitions of the clock. It is desired that when M = 1 the circuit should function as an up-counter (in 8421 BCD) and when M=0, as a down-counter. Design the combinational circuit interposed between the flip-flops so that the circuit works as desired. (i.e. find F as a function of Q,$$\overline Q $$, M, $$\overline M $$).

For the circuit shown in the figure below, sketch V₀ against time. Assume that all flip-flops are reset to zero before the clock is applied.

The circuit given below is a