The frequency of the clock signal applied to the rising edge triggered $$D$$ flip-flop shown in Fig. is $$10$$ $$kHz.$$ The frequency of the signal available at $$Q$$ is

The ripple counter shown in Fig. is made up negative edge triggered $$J$$-$$E$$ flips flops. The signal levels at $$J$$ and $$K$$ inputs of all the flip-flops are maintained at logic $$1$$. Assume that all outputs are cleared just prior to applying the clock signal.

$$(a)$$ Create a table of $${Q_0},{Q_1},{Q_2}$$ and $$A$$ in the format given below for $$10$$ successive
$$\,\,\,\,\,\,\,\,$$ input cycles of the clock $$CLK1.$$
$$(b)$$ Determine the module number of the counter.
$$(c)$$ Modify the circuit of Fig. to create a modulo$$-6$$ counter using the same
$$\,\,\,\,\,\,\,$$ components used in the figure.

The logic circuit used to generate the active low chip select $$(CS)$$ by an $$8085$$ microprocessor to address a peripheral is shown in Fig. The peripheral will respond to addresses in the range.

A series $$R-L-C$$ circuit has $$R = 50\Omega ;$$ $$L=100$$ $$\mu H$$ and $$C = 1\,\,\mu F.$$ The lower half power frequency of the circuit is